A multi-bus arbitration circuit has been known (for example, refer to Patent Document 1). When transfer destination buses of a plurality of requests do not conflict with each other, a transfer destination bus conflict determining part causes a data transfer executing part to execute data transfers for all the requests in parallel, and when they conflict with each other, leaves the processing to a transfer destination bus determining part. A request priority determining part in the transfer destination bus determining part compares priorities of request priority parameters regarding the plural requests to give an instruction to a cancel processing part in order to return a cancel to a bus arbitration circuit that has issued a low-priority request, and gives an execution instruction to the data transfer executing part in order to cause the execution of the data transfer of a high-priority request.
Further, a transaction queue for agent that operates according to a dynamic priority scheme has been known (for example, refer to Patent Document 2). The transaction queue operates according to a default priority scheme, and when a congestion event is detected, it uses a second priority scheme.
Further, there has been known a memory access control circuit that registers, in a queuing buffer, transactions each generated by a bus master and assigned an ID, and processes the transactions according to the order in which they are registered in the queuing buffer (for example, refer to Patent Document 3). A transaction detecting means recognizes the ID, and detects that a transaction from the bus master which influences performance by latency has been registered in the queuing buffer. When the transaction giving the influence is detected by the detecting means, a processing sequence change means processes this transaction first in precedence over transactions which are kept queuing.
Further, there has been known a bus connecting device that connects a first bus to which a memory storing various kinds of electronic data is connected and a second bus to which a plurality of control means accessing the memory are connected, and controls the accesses from the control means to the memory (for example, refer to Patent Document 4). A queuing means accumulates, in a queuing buffer, access requests to the memory which are transmitted from the control means, to sequentially process them. A bypass processing means processes a predetermined access request corresponding to predetermined processing requiring a real time property among the access requests to the memory which are transmitted from the control means, in precedence over the other access requests which are processed by the queuing means, by making the predetermined processing bypass the queuing buffer.
Patent Document 1: Japanese Laid-open Patent Publication No. 2000-267992
Patent Document 2: Japanese translation of PCT International Application Publication No. 2003-521029
Patent Document 3: Japanese Laid-open Patent Publication No. 2006-185198
Patent Document 4: Japanese Laid-open Patent Publication No. 2012-27577
In Patent Document 1, when transfer destination buses of a plurality of requests conflict with each other, an instruction is given to the cancel processing part in order to return a cancel to the bus arbitration circuit that has issued a low-priority request, and an execution instruction is also given to the data transfer executing part in order to cause the execution of the data transfer of a high-priority request. However, when there is no conflict, the data transfer executing part is made to execute the data transfers for all the requests in parallel, and accordingly a high-priority request is sometimes kept waiting until the processing of a low-priority request issued first is ended, and is not executed at once.